3 Months Internship in VLSI Design & Verification

This course is a thorough introduction to the Verilog language. The emphasis is on writing Verilog model, both behavioral and structural  source code  and Register Transfer Level (RTL).

5,000.00

Learn in-demand VLSI Design and Verification Methodologies like RTL design and UVM Methodologies and make them specialized in the advanced VLSI technology domains such as Design For Test, Low Power Verification, Analog Mixed Signal Verification etc

Course Content

  • Overview of Digital electronics & Number System, codes
  • Codes & its types Logic Gates
  • Combinational Circuits
  • Sequential Circuits
  • Overview of Verilog
  • Lexical Coventions & Testbench writing
  • RTL Coding
  • Operators
  • Verilog Processes, Assignments
  • Coding
  • Assignments
  • Lab practice on combinational cicuits(RTL)
  • Single port RAM
  • Dual port RAM
  • Overview to System Verilog
  • System Verilogs Data Types and memories
  • System Verilog Task and Function
  • Verification Plan
  • Overview of Universal Verification Methodology(UVM)
  • UVM factory
  • Stimulus Modeling and Phases
  • Reporting Mechanism

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