Certificate Course in VLSI Design & Verification
Learn in-demand VLSI Design and Verification Methodologies like RTL design and UVM Methodologies and make them specialized in the advanced VLSI technology domains such as Design For Test, Low Power Verification, Analog Mixed Signal Verification etc..
4 Months
Duration
100 Hours
Online Content + Live Session
Online
Mode
Live Sessions
By Industry Experts
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Batch Starts
Program Highlights
Designed for Professionals and Passouts
100+ Hours of Content
8 + Case Studies
Practical Capstone Project
25+ Mentorship Sessions from Industry Experts
Profile Building Workshops
Placement Assistance
Dedicated Student Success Mentor & Career Mentor for 360 Degree Support
Why Join Us
A proven course to dive into the programming of VLSI Design by World’s leading semiconductor companies.
Join our Online Internship Course on VLSI Design equipped with high end peripherals and easy integration capabilities to learn how to write code for frequently used peripherals and protocols such as Router 1×3, digital logics, AMBA, SPI, I2Cetc.
We offers systematic and easy to understand video lectures in order to ease self-learning.
Who Should Join The Course?
Students & Professionals who
- are total beginner to the Verilog hdl.
- would like to enhance his/her career in VLSI Design applications
- would love to program for basic as well as advanced applications
Hex-N-Bit Advantage
Self Paced eLearning Content
A highly quality & extremely informative self-paced learning content that will help student to build technical skill.
Live Sessions
An interactive live session with highly experience mentors in order to make the core technical concepts crystal clear & addressing any technical doubts.
Labs & Assignments
Competitive assignment which will test your skill & learning
Duration : 1 Assignment per week
Quizes
A time bound Quiz that will help you to manage the pressure while chasing any deadline for product development
Mini Projects
Some interesting & engaging projects will be assigned to students once in a month where they have to work on real time case study. These projects will be graded by the mentors with some suggestions(if required)
Industry Exposure
Regular Mentorship from Industry Experts
Industry Live Connect- Mentor Support
A live projects like SmartCarx, LoRA enabled Smart home , AMBA protocol etc will be covered in order to ink the industry touch during their certification course
Capstone Projects
Finally , during the last month of their certification course, they will have to work on one big and highly extensive academic project that is undertaken by student as a final task in their certificate programs. Capstone project will be done under the supervision of mentor.
Certification
Once the student submit the capstone project then the candidate would be liable to get the certificate.
Syllabus
- Overview of Digital Electronics
- Overview of Number System
- Codes & its Types
- Logic Gates
- Combinational Circuits
- Sequential Circuits
- Overview of Verilog
- Lexical Conventions & Test Bench Writing
- RTL Coding
- Operators
- Verilog Processes
- Creating RTL & Test Bench
- Single Port RAM
- Dual Port RAM
- FIFO (First In First Out)
- Overview of System Verilog
- Data Types
- Memories
- Task & Functions
- Interfaces
- Clocking Blocks
- Overview of Classes
- Objects
- Advance OOPS Concepts
- TB Infrastructure
- Virtual Classes
- Generator
- Monitor
- RAM- TB
- Coverpoints & Covergroups
- Introduction to UVM
- UVM Factory
- Stimulus Modeling
- Phases
- Reporting Mechanism
- UVM Monitor
- UVM Agent
- Creating Agent
- Transaction Level Modeling
- UVM Configuration
- Creating TB Components
- UVM Sequences
- Introduction to UVM Callbacks
- Creating Scoreboard
- Test Bench Verification Plan & Directory Summary
- Interfaces & Clocking Blocks
- Hierarchical Connections Between Different Test Bench Components
- Factory Overriding Method in Test Bench Components
- UVM Topology Printing using Different Built-in Functions
Hours of Content + Live Session
Case Studies & Projects
Live Sessions
Assignments
Tools & Libraries
Capstone Project
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Benefits you will take away
- Gain understanding of verilog hdl features and applications.
- Getting familiar with most frequently used peripherals for basic applications.
- Video lectures for hands on session and typical applications based on that.
- Guidance for developing the project based learning.
- Duration: 4 Months
- Centralized teams
- Live Sessions
- Project Support
- Industry mentorship